Integrated multi-function analog circuit including voltage, current, and temperature monitor and gate-driver circuit blocks

ABSTRACT

An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of co-pending U.S. patent application Ser. No. 11/562,049, filed Nov. 21, 2006, which is a Continuation of U.S. patent application Ser. No. 11/016,699, filed Dec. 17, 2004, now issued as U.S. Pat. No. 7,138,824, which is a Continuation-in-Part of U.S. patent application Ser. No. 10/843,701, filed May 10, 2004, now issued as U.S. Pat. No. 7,170,315, all of which are hereby incorporated by reference as if set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuits. More particularly, the present invention relates to an integrated circuit device including a multi-function analog circuit that contains voltage, current, and temperature monitor blocks and a gate-driver circuit block.

2. Background

Integrated circuits that perform both analog and digital functions are known in the art. Recent developments include system-on-a-chip integrated circuits that include programmable logic that may be programmably coupled to one or more analog circuits disposed on the same integrated circuit, multichip module or flip-chip assembly.

Traditionally, FPGAs and other programmable logic devices (PLDs) have been limited to providing digital logic functions programmable by a user. Recently, however, FPGA manufacturers have experimented with adding application specific integrated circuit (ASIC) blocks onto their devices (See, e.g., U.S. Pat. No. 6,150,837). Such ASIC blocks have included analog circuits (see U.S. Pat. No. 5,821,776). In addition, ASIC manufacturers have embedded programmable logic blocks in their devices to add programmable functionality to otherwise hardwired devices (See, e.g., devices offered (or formerly offered) by Triscend Corporation, Adaptive Silicon Inc., and Chameleon Systems.

SUMMARY OF THE INVENTION

An integrated multi-function analog circuit includes at least one MOSFET gate-drive circuit coupled to a first I/O pad. At least one voltage-sensing circuit is coupled to a second I/O pad. At least one current-sensing circuit is coupled to the second I/O pad and a third I/O pad. At least one temperature-sensing circuit is coupled to a fourth I/O pad.

According to one aspect of the invention, at least one of the first through fourth I/O pads may be used to provide a digital input to the integrated circuit. According to another aspect of the invention, the gate-drive circuit is configured to drive either p-channel or n-channel external transistors. According to another aspect of the invention, the gate-drive circuit is also configured to provide a switched ground for driving an external load. According to another aspect of the invention, a scaling circuit may be provided between at least one of the second third and fourth I/O pads and the sensing circuits to which they are connected. According to another aspect of the invention, the outputs of the sensing circuits according to the present invention may be input to an analog-to-digital converter to produce a digital output to be used by digital circuitry on the integrated circuit.

A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings, which set forth an illustrative embodiment in which the principles of the invention are utilized.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of an illustrative integrated circuit employing the integrated multi-function analog circuit of the present invention.

FIG. 2 is a block diagram of one illustrative embodiment of an integrated multi-function analog circuit according to one aspect of the present invention.

FIG. 3 is a diagram of a pre-scaler circuit that can scale external voltages by one of eight factors.

FIG. 4 is a diagram of an illustrative configuration for the amplifier in the current-sensing circuit of FIG. 2.

FIG. 5 is a diagram of an illustrative temperature sensing circuit that may be usefully employed in the multi-function analog circuit of FIG. 1.

FIG. 6 is a diagram of an illustrative gate drive circuit that may be usefully employed in the multi-function analog circuit of FIG. 1.

FIG. 7 is a schematic diagram of an illustrative digital input circuit that may be coupled to the same I/O pad a one of the sensing circuits of the present invention.

FIG. 8 is a schematic diagram of an alternative illustrative gate-drive circuit that may be usefully employed in the multi-function analog circuit of FIG. 1.

DETAILED DESCRIPTION

Those of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.

Referring first to FIG. 1, an integrated circuit 10 according to the present invention includes a gate-driver circuit 12, a voltage-sensing circuit 14, a current-sensing circuit 16, and a temperature-sensing circuit 18. Gate-driver circuit 12 is coupled to I/O pad 20, voltage-sensing circuit 14 is coupled to I/O pad 22, current-sensing circuit 16 is coupled to I/O pad 24, and temperature-sensing circuit 18 is coupled to I/O pad 26.

Integrated circuit 10 also includes programmable digital circuits 28 and a program control block 30. Programmable digital circuits 28 may include, for example, a field-programmable gate array (FPGA). Program control block 30 may include control circuitry for programming the FPGA and controlling the functions and connections in the gate-driver circuit 12, voltage-sensing circuit 14, current-sensing circuit 16, and temperature-sensing circuit 18.

Programmable digital circuits 28 may be coupled to a plurality of I/O pads 32, 34, 36, and 38 that serve as inputs and outputs for digital signals handled by programmable digital circuits 28. Persons of ordinary skill in the art will appreciate that the two input I/O pads 32 and 34 and the two output I/O pads 36 and 36 are illustrative and the actual number will vary as needed by the designer. Such skilled persons will also appreciate that I/O pads 32, 34, 36, and 38 may not be hardwired as inputs and outputs but may be designated as inputs and outputs by programming connections between them and the programmable digital circuits 28 as is well known in the art. I/O pads 20, 22, 24, and 26 may be configured as digital inputs that may be coupled to the programmable digital circuitry through lines 46.

Program control block 30 may also include programmable elements, such as non-volatile memory cells, volatile memory cells such as SRAM, antifuses, or the like, necessary to define the functions and connectivity of the programmable logic inside programmable digital circuits 28 and the gate-driver circuit 12, voltage-sensing circuit 14, current-sensing circuit 16, and temperature-sensing circuit 18. Persons of ordinary skill in the art will realize that program control block 30 is conceptual and that the individual programmable elements may be physically distributed throughout the integrated circuit 10 in a known manner to control the programmable circuit elements. Program control block 30 is shown coupled to a representative I/O pad 40. Persons skilled in the art will appreciate that single I/O pad 40 may be understood to represent a JTAG port or other known means for programming the programmable elements on integrated circuit 10.

The outputs of voltage-sensing circuit 14, current-sensing circuit 16, and temperature-sensing circuit 18 are coupled to A/D converter 42 through multiplexer 44. The address inputs of multiplexer 44 may be driven by lines 48 from circuits configured in programmable digital circuits 28 to allow dynamic selection between the outputs of voltage-sensing circuit 14, current-sensing circuit 16, and temperature-sensing circuit 18. In other embodiments of the invention where dynamic selection of the signal source for A/D converter 42 is not necessary, the address inputs of multiplexer 44 may be driven from program control circuitry 30.

The set of multi-function analog circuits shown in FIG. 1 has four members including gate-driver circuit 12, voltage-sensing circuit 14, current-sensing circuit 16, and temperature-sensing circuit 18. Persons of ordinary skill in the art will realize that FIG. 1 is illustrative only, and a set of analog I/O circuits in an actual integrated circuit may have fewer or more members.

Referring now to FIG. 2, a block diagram shows one illustrative embodiment of an integrated multi-function analog circuit 50 according to one aspect of the present invention. Multi-function analog circuit 50 includes a voltage-sensing block 52 coupled to I/O pad 54. I/O pad 54 may either have a direct connection to the input of A/D converter 42 of FIG. 1 (or one input of its input multiplexer 44), or may be connected to it through a buffered prescaler circuit 56. Prescaler circuit 56 may have a programmable gain set to 1 of n selectable values as will be disclosed further herein. Multiplexer 58 is employed to select between the direct input or the prescaled input. The select inputs of multiplexer 58 may be controlled from the programmable digital circuits 28 by control lines 48 (FIG. 1). According to another aspect of the present invention, I/O pad 54 can be configured through digital input circuit 60 as a low-performance digital input to the programmable digital circuits 28 of FIG. 1.

A second member 62 of the set may be a current-monitor input block coupled to I/O pad 64. Like I/O pad 54, I/O pad 64 may either have a direct connection to the input of A/D converter 42 (or one input of its input multiplexer 44), or may be connected to it through a buffered prescaler 66. Like prescaler 56, prescaler 66 may have a programmable gain set to 1 of n selectable values as will be disclosed further herein. Multiplexer 68 is employed to select between the direct input from I/O pad 64 or the prescaled input. The select inputs of multiplexer 68 may be controlled from the programmable digital circuits 28 by control lines 48 (FIG. 1). Like I/O pad 54, I/O pad 64 can be configured through digital input circuit 70 as a low-performance digital input to the programmable digital circuits 28

In addition to the functions that are identical to that for I/O pad 54, current-sensing circuit 62 may be used to measure the voltage difference between I/O pad 54 and I/O pad 64. This may be used to measure a voltage drop across a small external resistor in series with an external power supply. I/O pad 64 is connected to one input of an amplifier 72. The other input of amplifier 72 is coupled to I/O pad 54. The output of amplifier 72 is presented to a third input of multiplexer 68. If a low value (e.g., 0.1 ohms) resistor (not shown in FIG. 2) is coupled between I/O pads 54 and 62, and a voltage supply potential is coupled to I/O pad 54 and a load is coupled to I/O pad 64, the voltage drop across that resistor can be sensed and amplified by amplifier 72. That voltage drop is directly proportional to the current flowing through the resistor. An illustrative configuration for amplifier 160 is shown and described with reference to FIG. 4.

A third member 74 of the set may be a temperature-sensor input block coupled to I/O pad 76. Like I/O pad 54, I/O pad 76 may either have a direct connection to the input of A/D converter 42 (or one input of its input multiplexer 44), or may be connected to it through a buffered prescaler 78. Like prescaler 56, prescaler 78 may have a programmable gain set to 1 of n selectable values as will be disclosed further herein. Multiplexer 80 is employed to select between the direct input from I/O pad 76 or the prescaled input. The select inputs of multiplexer 80 may be controlled from the programmable digital circuits 28 by control lines 48 (FIG. 1). Like I/O pad 54, I/O pad 76 can be configured through digital input circuit 82 as a low-performance digital input to the programmable digital circuits 28.

In addition to the functions that are identical to that for I/O pad 54, temperature-sensing circuit 74 may be used as a temperature monitor for a signal on I/O pad 76. This temperature-sensing circuit 74 may be configured to measure temperature of an external diode by taking advantage of the temperature behavior of the I-V characteristics of a diode. A temperature-sensor circuit 84 may also be coupled to an input of multiplexer 80. An integrated circuit according to the present invention may be supplied with a plurality of temperature monitor circuits. According to one embodiment of the invention, a number of temperature sensors are for measuring external temperature (e.g., the junction temperatures of other ICs or air temperature) and one for measuring its own junction temperature. Temperature sensor circuit 84 is explained in more detail with reference to FIG. 5.

A fourth member 86 of the set may be a gate-driver output block coupled to I/O pad 88. Power MOSFET gate driver circuit 86 drives I/O pad 88 from the programmable digital circuits 28. I/O pad 88 may be coupled to I/O pad 64 and/or I/O pad 76 through either of pullup resistors 92 and 94, respectively. Persons of ordinary skill ion the art will realize that resistors 92 and 94 are optional. An optional ramp resistor 96 may be coupled to I/O pad 64 or I/O pad 76. Gate driver circuit 90 is explained in more detail with reference to FIG. 7.

Referring now to FIG. 3, a diagram shows an illustrative pre-scaler circuit 100 that can scale external voltages by one of eight factors. According to one embodiment of the present invention, the pre-scaler circuits 56, 66, and 78 are provided to scale external voltages up or down. In FIG. 3, a pre-scaler circuit 100 is shown that can scale both positive and negative external voltages by one of eight factors. The pre-scaler circuit 100 of FIG. 3 can be used in voltage monitor functions or in any analog input functions. The pre-scaler circuit 100 may be based upon a current mirror circuit.

When an external positive voltage is applied to I/O pad 54, p-channel MOS transistor 102 is turned on and n-channel MOS transistor 104 is turned off through operational amplifier 106. The current through n-channel MOS transistor 108 having a channel width WI is mirrored and scaled through the array 110 of n-channel MOS transistors having a cumulative width of W2. Thus, Vout=VI*(W2/W1).

When an external negative voltage is applied to I/O pad 54, p-channel MOS transistor 102 is turned off and n-channel MOS transistor 104 is turned on. The current through p-channel MOS transistor 112 is the same as the current through n-channel MOS transistor 104 and is mirrored through p-channel MOS transistor 114. This current is in turn mirrored by n-channel MOS transistor 116 having a channel width of W3. The current through n-channel MOS transistor 116 is mirrored and scaled through the array 118 of n-channel transistors having a cumulative width of W4. Thus, Vout=VI*(W4/W3).

The cumulative widths W2 and W4 of the n-channel MOS transistor arrays 104 and 118 are determined by which of the upper n-channel MOS transistors in each array are turned on by one of the lower transistors in the array. Each upper transistor has a different width and the gate of each lower transistor is driven from the output of decoders 120 (for positive scaling) and 122 (for negative scaling). The widths of n-channel MOS transistors 108, 116, and n-channel MOS transistor arrays 110 and 118 are selected to produce the desired scaling factors.

The control lines of decoder circuits 120 and 122 are driven from on-chip information that may be generated from, for example, an FPGA array, or a state machine. The outputs of n-channel MOS transistor arrays 110 and 118 are coupled together to the inverting input of operational amplifier 124. Resistor 126 sets the gain of operational amplifier 124.

According to one aspect of the invention, the following voltage-scaling factors: 0.20161, 0.40322, 0.80645, 1.6129, 3.2258, 6.45161, 12.90322, and 25.80645 have been found to be particularly useful. This is particularly useful where the full-scale voltage of A/D converter 42 of FIG. 1 is 3.3V. The choice of these eight scaling factors is controlled by three binary control signals coming from the programmable digital circuits 28. Using these factors 16V can be scaled down to 3.3V using the factor 0.20161 (16*0.20161=3.3) and 125 mv can be scaled up to 3.3V using the factor 25.80645 (0.125*25.80645=3.3). Hence the function of the pre-scaler is to convert input voltages into ranges that are acceptable by the A/D converter 42. The reason for employing the exemplary scaling factors recited herein is for user convenience to achieve correspondence between the digital output of the A/D converter 42 and one-millivolt steps. From an examination of this disclosure, persons of ordinary skill in the art will appreciate that any number of different scaling factors may be selected.

An illustrative configuration for amplifier 72 of FIG. 2 is shown and described with reference to FIG. 4. External resistor 130 is shown coupled between I/O pads 54 and 62. By the initial positions of switches 132, 134, 136, and 138 (shown in FIG. 9), the offset value of the operational amplifier 140 is stored in capacitor 142 so that the output of the operational amplifier 140 is approximately at ground. Also the capacitors 144 and 146 are charged to the voltage level, which is at the right side of the external resistor 130, and the non-inverting input of the operational amplifier 140 is at ground. The inverting input of operational amplifier 140 is at virtual ground. Switches 122, 124, 126, and 128 are then switched in order (first switch 122, then switch 134, then switch 136, then switch 138). After all the switches 132, 134, 136, and 138 are at their new positions, the voltage drop across the external resistor 130 is amplified by the operational amplifier 140 with a gain defined by (C146+C134)/C134. The output voltage of the operational amplifier 140 is applied to the input of the ADC. Since the value of the external resistor value is known, the current through the external resistor is known. The configuration of the circuit of FIG. 4 has the advantage of avoiding amplifying the voltage offset of operational amplifier 140.

Referring now to FIG. 5, temperature-sensor circuit 84 is explained in more detail. This circuit forces two different currents through a diode and measures the voltage drop difference across the diode. It then amplifies this voltage by a factor of five and sends it to the ADC. This amplified voltage difference directly corresponds to temperature (in ° K). Persons of ordinary skill in the art will appreciate that, while FIG. 5 shows an external diode, an internal diode could be employed to measure on-chip temperature.

For example, as shown in FIG. 5, a voltage difference of 59.6 mV (corresponding to diode temperature of 25° C.) is measured by sequentially forcing 10 uA and 100 uA across diode 150. This is amplified 5×—which gives 298 mV—which corresponds to 298 K (25 C.). Diode 150 is coupled to I/O pad 76. Two current-generating circuits are shown, allowing the diode 150 to be oriented in either direction. The first current-generating circuit which sources current includes a first leg including p-channel MOS transistors 152, 154, and 156 coupled in series between a supply potential of +3.3 VDC and the I/O pad 76. The gate of transistor 152 is coupled to a positive bias potential. The gate of transistor 154 is coupled to ground and the gate of transistor 156 is coupled to a Source/Sink control signal. The sizes of transistors 152, 154, and 156 and the value of the positive bias potential are chosen to cause 10 μA to flow (source) through diode 150.

The second leg in the first current-generating circuit includes p-channel MOS transistors 158, 160, and 162 coupled in series between the supply potential of +3.3 VDC and the I/O pad 76. The gate of transistor 158 is coupled to the positive bias potential. The gate of transistor 160 is coupled to a control signal “S” and the gate of transistor 162 is coupled to the Source/Sink control signal. The sizes of transistors 158, 160, and 162 and the value of the positive bias potential are chosen to cause an additional 90 μA to flow (source) through diode 150.

Similarly, The second current-generating circuit which sinks current includes a first leg including n-channel MOS transistors 164, 166, and 168 coupled in series between a supply potential of −3.3 VDC and the I/O pad 76. The gate of transistor 164 is coupled to a negative bias potential. The gate of transistor 166 is coupled to a positive voltage and the gate of transistor 168 is coupled to the Source/Sink control signal. The sizes of transistors 164, 166, and 168 and the value of the negative bias potential are chosen to cause 10 μA to flow (sink) through diode 150.

The second leg in the first current-generating circuit includes n-channel MOS transistors 170, 172, and 174 coupled in series between the supply potential of −3.3 VDC and the I/O pad 76. The gate of transistor 170 is coupled to the negative bias potential. The gate of transistor 172 is coupled to the control signal “S” and the gate of transistor 174 is coupled to the Source/Sink control signal. The sizes of transistors 170, 172, and 174 and the value of the negative bias potential are chosen to cause 90 μA to flow (sink) through diode 150.

If the Source/Sink control signal is low, the current sourcing transistors operate. If the Source/Sink control signal is high, the current sinking transistors operate. In either case, the first leg of the circuit (either transistors 152, 154, and 156 or transistors 164, 166, and 168) are turned on, sourcing or sinking 10 μA through diode 150. When the “S” (or “S!”) signal is asserted, the second leg of the circuit (either transistors 158, 160, and 162 or transistors 170, 172, and 174) is also turned on, sourcing or sinking a total of 100 μA through diode 150.

The remaining components of the circuit include operational amplifier 176 having its non-inverting input grounded, capacitor 178 coupled between I/O pad 76 and the inverting input of operational amplifier 176, and capacitor 178, coupled between the inverting input of operational amplifier 176 and its output through n-channel MOS transistor 182. In the example of FIG. 5, capacitor 178 has five times the capacitance of capacitor 180, which determines the gain of the circuit. Capacitor 180 stores and thus cancels the offset of operational amplifier 176.

The common connection of capacitor 180 and transistor 182 is coupled to ground through n-channel MOS transistor 184. The gate of transistor 182 is coupled to a control signal Y! and the gate of transistor 184 is connected to a control signal Y. An n-channel MOS transistor 186 is coupled between the inverting input sand the output of operational amplifier 176 and has its gate coupled to a control signal X. An n-channel MOS transistor 188 is coupled to the inverting input of operational amplifier 176 and has its gate coupled to a control signal X!. The relative timing of the control signals X, Y, Y! and S is shown at the right side of FIG. 5. The difference in diode voltage before and after the timing sequence is amplified by the circuit gain and appears at the output of the operational amplifier 166, corresponding to the absolute temperature.

Persons of ordinary skill in the art will appreciate that the actual current source and sink levels, supply voltage values circuit gains can be changed without changing the nature of the circuit operation. In addition, such skilled persons will realize that, while a single-ended circuit is shown in FIG. 5, a differential circuit could be used to measure the voltage across the diode.

Referring now to FIG. 6, the operation of a gate driver circuit like the one of FIG. 2 is explained in more detail. External power MOSFET 190 has its source coupled to supply potential 192. Its gate is coupled to I/O pad 88 and its drain is coupled to I/O pad 64 or 76 (see FIG. 2). If supply potential 192 is positive, power MOSFET 190 will be a p-channel device and if supply potential 192 is negative, power MOSFET 190 will be an n-channel device. Resistor 92 or 94 (again see FIG. 2) may be disposed outside of the integrated circuit device and are used to assure that the power MOSFET 190 will be turned off unless a gate drive signal is supplied at I/O pad 88.

Operational amplifier 194 drives the gate of p-channel MOS gate-drive transistor 196. The drain of p-channel MOS gate-drive transistor 196 is coupled to I/O pad 88. The source of p-channel MOS transistor gate-drive transistor 196 is coupled to a positive supply potential through p-channel MOS enable transistor 198. The non-inverting input of operational amplifier 194 is coupled to the drain of power MOSFET 190 via I/O pad 64 (or 76) through resistor 200. The inverting input of operational amplifier 198 is coupled to capacitor 202 driven by constant-current source 204.

Similarly, operational amplifier 206 drives the gate of n-channel MOS gate-drive transistor 208. The drain of n-channel MOS gate-drive transistor 208 is coupled to I/O pad 88. The source of n-channel MOS transistor gate-drive 208 is coupled to a negative supply potential through n-channel MOS enable transistor 210. The inverting input of operational amplifier 206 is coupled to the drain of external power MOSFET 190 via I/O pad 64 (or 76) through resistor 200. The non-inverting input of operational amplifier 206 is coupled to capacitor 212 driven by constant-current source 214. The non-inverting input of operational amplifier 194 and the inverting input of operational amplifier 206 are coupled to ground through resistor 216.

In the example shown in FIG. 6 where an n-channel MOS power transistor 190 is to be driven, p-channel enable transistor 198 is turned on. To turn on n-channel MOS power transistor 190, current source 204 is turned on and charges capacitor 202 at a linear rate. The voltage on capacitor 202 is amplified with a negative gain, producing a decreasing ramp voltage at the output of operational amplifier 194. This causes a decreasing ramp voltage at the drain of p-channel gate drive transistor 196 to turn on p-channel MOS power transistor 190. The final gate voltage on the external MOS power transistor 190 is established by the IR drop across the gate-to-source resistor 92 or 94 and is determined by the current through the p-channel enable transistor 198. If it is desired to turn on an external p-channel MOS power transistor, n-channel enable transistor 210 is turned on, current source 214 is turned on and charges capacitor 212 at a linear rate. The voltage on capacitor 212 is amplified with a positive gain, producing an increasing ramp voltage at the output of operational amplifier 206. This causes an increasing ramp voltage at the drain of n-channel gate drive transistor 208 to turn on the external p-channel MOS power transistor. The feedback provided to the operational amplifiers 194 and 206 through resistor 200 assures controlled ramp rates on the load.

FIG. 7 is a schematic diagram of an illustrative digital input circuit like 60, 70, or 82 of FIG. 2 that may be coupled to the same I/O pad as one of the sensing circuits of the present invention. Buffer 220 is shown coupled to illustrative I/O pad 22. Buffer 220 is designed with hysteresis at its input as is known in the art. The output of buffer 220 is coupled to one input of AND gate 222. The other input of AND gate 222 is coupled to the output of level-shifter circuit 224. Level-shifter circuit 224 is configured to shift logic levels from those used in the programmable digital circuits 28 of FIG. 1 (such as 1.5V) to off-chip logic levels (such as 3.3V). The output of AND gate 222 is coupled to the input of level-shifter circuit 226. Level-shifter circuit 226 is configured to shift logic levels from off-chip logic levels (such as 3.3V) to those used in the programmable digital circuits 28 of FIG. 1 (such as 1.5V).

The circuit of FIG. 7 allows the digital input to be enabled. If a logic zero is presented to the input of level-shifter circuit 224, the output of AND gate 222 is forced to zero. If a logic one is presented to the input of level-shifter circuit 224, the output of AND gate 222 follows the logic state at the I/O pad 22.

Referring now to FIG. 8, a schematic diagram shows an alternative illustrative gate-drive circuit that may be usefully employed in the multi-function analog circuit of FIG. 1. The circuit of FIG. 8 not only provides gate drive for external devices but can also pull I/O pad 88 down to ground if the voltage at I/O pad 88 is positive and can pull I/O pad 88 up to ground if the voltage at I/O pad 88 is negative.

I/O pad 88 is coupled to the drain of n-channel MOS transistor 230. The source of n-channel MOS transistor 230 is coupled to ground. The gate of n-channel MOS transistor 230 is coupled to an enable signal line 232 that is driven from an output in the programmable digital circuit 28 of FIG. 1. If the signal on the enable line 232 is at ground, n-channel MOS transistor 230 is turned off. If the signal on enable line 232 is at a logic one, n-channel MOS transistor 230 is turned on and can pull I/O pad 88 down to ground if the voltage at I/O pad 88 is positive and can pull I/O pad 88 up to ground if the voltage at I/O pad 88 is negative.

Current-source circuit 234 is also coupled to I/O pad 88. It has an enable input line 236 and a magnitude input bus 238. Current-sink circuit 240 is also coupled to I/O pad 88. It has an enable input line 242 and a magnitude input bus 244. The enable lines and magnitude input busses 236, 238, 242, and 244 are driven from an output in the programmable digital circuit 28 of FIG. 1.

When enabled, current-source circuit 234 and current-sink circuit 240 may, respectively, source current to or sink current from I/O pad 88. Preferably, several different current levels may be programmably current limited. In an illustrative embodiment of the invention, these current levels may be, for example, 1 μA, 3 μA, 10 μA, and 30 μA. Specific embodiments of the invention will employ current levels as a matter of design choice.

In application, an external MOS power transistor has its gate coupled to I/O pad 88. An external resistor is coupled between the source of the external transistor and I/O pad 88. For example, external n-channel MOS transistor 246 is shown with its source coupled to a potential V− and its drain coupled to a load 248. A resistor 250 is coupled between the source and gate of external n-channel MOS transistor 246. A dashed line indicates a connection between the gate of external n-channel MOS transistor 246 and I/O pad 88.

To drive external n-channel MOS transistor 246, enable lines 232 and 242 are disabled to disable n-channel MOS transistor 230 and current sink circuit 240. Enable line 236 is enabled to enable current source circuit 234. Data representing the desired current source magnitude are placed on magnitude bus 238.

Similarly, external p-channel MOS transistor 252 is shown with its source coupled to a potential V− and its drain coupled to a load 254. A resistor 256 is coupled between the source and gate of external p-channel MOS transistor 252. A dashed line indicates a connection between the gate of external p-channel MOS transistor 252 and I/O pad 88.

To drive external p-channel MOS transistor 252, enable lines 232 and 236 are disabled to disable n-channel MOS transistor 230 and current source circuit 234. Enable line 242 is enabled to enable current sink circuit 240. Data representing the desired current source magnitude are placed on magnitude bus 244.

While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims. 

1. An integrated multi-function analog circuit including: at least one MOSFET gate-drive circuit coupled to a first I/O pad. at least one voltage-sensing circuit coupled to a second I/O pad; at least one current-sensing circuit coupled to the second I/O pad and a third I/O pad; and at least one temperature-sensing circuit coupled to a fourth I/O pad. 